Monday, September 22, 2014

TI's 100G transimpedance amplifier drives high performance in optical networking systems

DALLAS, USA: Texas Instruments (TI) introduced its first transimpedance amplifier (TIA) for the 100G optical networking market.

As a key component of the system, the ONET2804T brings high levels of sensitivity with negligible cross-talk penalty and low input-referred noise (IRN) to provide stable and robust communication in hot-pluggable transceivers.

The newest member of TI's broad optical networking portfolio, the 100G TIA serves parallel optical interconnects in applications with data rates of up to 28 Gbps, such as optical line cards, point-to-point microwave backhauls and video over fiber.

MediaTek Labs developer program for simplified creation of portable and IoT devices

HSINCHU, TAIWAN: MediaTek launched Labs on the market, a global initiative, which developers of any background knowledge or knowledge of portable devices and IoT (Internet of can develop things).

The new program provides developers, manufacturers and service providers Software Development Kits (SDKs), Hardware Development Kits (HDKs), technical documentation, and technical and managerial support.

"With the launch of MediaTek Labs we open for everyone - from amateurs on students to professional developers and designers - a new world of possibilities in which creativity and innovation are no limits," says Marc Naddell, VP of MediaTek Labs. "We are convinced that the benefits of activities MediaTek Labs innovations will lead the next wave of consumer gadgets and apps that will cure billions of things and people around the world."

The Labs Developer Program includes the LinkIt-Entwickler platform based on the MediaTek Aster (MT2502) chipset based. The LinkIt developer platform is one of the most effectively networked platforms with outstanding integration for the package size and requires no additional hardware for connectivity.

With LinkIt and the proven reference model for developing design of MediaTek prototype portable and IoT devices can be easily and inexpensively created. The LinkIt platform consists of the following components:

Vesper launches with very high SNR MEMS mic tech

BOSTON, USA: Intending to improve the smallest audio component found in smartphones, wearables and Internet of Things (IoT) devices, a new Boston-based sensor company called Vesper has designed a microphone that will enhance consumers' acoustic experience with voice capture and sound recording.

Though such microphones are virtually invisible to consumers, the market for the highest-performance devices is huge: the research firm IHS predicts that it will reach $718 million by 2017i.

Vesper's microphone technology offers the highest signal-to-noise ratio (SNR) in ultra-compact form factors for consumer microphones: 70 db SNR, which is the key determining factor in acoustic performance.

Consumers demand a better acoustic experience with their mobile devices. However, current MEMS microphone technology has been lacking, limiting the quality of always-on voice command, which is prone to high rates of error, and high-fidelity sound recording, particularly in noisy environments.

Users cite 10 percent smaller design sizes with latest releases of Synopsys' Design Compiler

MOUNTAIN VIEW, USA: Synopsys Inc. announced that multiple customers have achieved smaller area using the latest releases of its Design Compiler RTL synthesis solution, a key component of Synopsys' Galaxy Design  Platform.

Aggressive area optimization is critical for designers across a wide range of electronic applications to either lower system costs or implement additional functionality without increasing die size. Innovations in the latest releases include advanced optimizations operating with and without physical information, which lower power and produce smaller, more routable designs without impacting timing.

"Minimizing area and meeting timing requirements enables us to differentiate and deliver value in a highly competitive multi-functional product marketplace," said Michihiro Okada, GM of the Software 3 R&D Division, Corporate Software Development Division at KYOCERA Document Solutions Inc., a leading manufacturer of document imaging solutions and document managing systems.

"Design Compiler's new monotonic area optimization reduced design area by 10 percent for multiple designs while meeting timing requirements and lowering leakage power. This allowed my design team to implement additional functionality without an increase in die cost."

"As a leader in mixed-signal semiconductors for the automotive, industrial and consumer markets, reducing die size is critical to meeting our  business objectives," said Armin Kemna, director Design Support at Elmos Semiconductor.  "We are seeing up to 10 percent reduction in gate count simply by using the latest release of Design Compiler. In addition, technology links between Design Compiler and IC Compiler provided early insight into physical challenges and helped us stay on schedule."

Design Compiler includes new optimization technologies that monotonically reduce design area and leakage power by an average of 10 percent while maintaining timing quality of results (QoR). These area optimizations operate on new or legacy design netlists, with or without physical information and at all process nodes.

Utilizing this new capability, in conjunction with new congestion optimizations, designers can significantly reduce die area and ease design closure without impacting any other QoR metrics. In addition, new RTL analyses and cross probing capabilities accelerate design schedules.

"Smaller die size and shorter design schedules continue to be key requirements for our customers designing at both established and emerging process nodes," said Bijan Kiani, VP of marketing for Synopsys' Design Group. "These new technologies for smaller area and lower power consumption help our customers to be more competitive in their market segments, while strengthening Design Compiler's position as the synthesis tool of choice for designers worldwide."

Altera and Baidu collaborate on FPGA-based acceleration for cloud data centers

NEW YORK, USA: Altera Corp. and Baidu, China’s largest online search engine, are collaborating on using FPGAs and convolutional neural network (CNN) algorithms for deep learning applications set to play a critical role in the development of more accurate and faster online search.

Altera is demonstrating its work with Baidu at the High Performance Computing (HPC) for Wall Street conference in New York City, taking place on September 22, 2014.

The Altera-Baidu demonstration (booth #215B) illustrates how much faster image classification can take place using FPGA-accelerated CNNs. In key search functions, such as image classification and recognition tasks, CNNs are considered to be the state-of-the-art and provide record-setting accuracy.

Baidu is leveraging Altera Stratix V FPGAs and the Altera SDK for OpenCL, which achieved Khronos OpenCL conformance testing certification in May 2013, to dramatically simplify the implementation of parallel processing applications.

Baidu Research distinguished scientist, Dr. Ren Wu, said: “Baidu is a pioneer and leader in both deep learning and heterogeneous computing, and we believe FPGA acceleration has great potential. OpenCL support is a game changer and will help FPGAs penetrate the mainstream heterogeneous computing world. It opens doors for countless opportunities.”

Altera’s data center technology offerings are based on the company’s high performance Stratix V and Arria 10 FPGAs, and next-generation Stratix 10 FPGAs and SoCs, which are manufactured using the Intel 14 nm Tri-Gate process and feature Altera’s high-performance HyperFlex architecture.

Altera’s FPGAs combine unprecedented reconfigurable logic with on-chip memory and DSP blocks, enabling the high performance and flexibility required by the demanding data center environment.

“Baidu and Altera are demonstrating a compelling heterogeneous computing approach to CNN algorithm acceleration,” said Altera Compute and Storage Business Unit director, Michael Strickland.

“The programmability and features, such as hard IEEE 754 floating point multipliers and adders in Altera FPGAs, enable servers and data centers to keep up and evolve with complex requirements in search, big data and deep learning.”

Vesper plans to disrupt massive market for MEMS microphones

BOSTON, USA: Intending to improve the smallest audio component found in smartphones, wearables and Internet of Things (IoT) devices, a new Boston-based sensor company called Vesper has designed a microphone that will enhance consumers' acoustic experience with voice capture and sound recording.

Though such microphones are virtually invisible to consumers, the market for the highest-performance devices is huge: the research firm IHS predicts that it will reach $718 million by 2017i.

Vesper's microphone technology offers the highest signal-to-noise ratio (SNR) in ultra-compact form factors for consumer microphones: 70 db SNR, which is the key determining factor in acoustic performance.

Consumers demand a better acoustic experience with their mobile devices. However, current MEMS microphone technology has been lacking, limiting the quality of always-on voice command, which is prone to high rates of error, and high-fidelity sound recording, particularly in noisy environments.

Industry’s biggest scaler vendors pledge support for AMD’s Project FreeSync

SUNNYVALE, USA: AMD announced collaborations with scaler vendors MStar, Novatek and Realtek to build scaler units ready with DisplayPort Adaptive-Sync and AMD’s Project FreeSync by the year end.

“Since the dawn of hardware-accelerated graphics, gamers dreamed of liquid smooth gameplay free of stuttering and tearing,” said Matt Skynner, corporate VP and GM, Graphics Business Unit, AMD. “AMD’s Project FreeSync is aimed at realizing that vision with an open, standardized and license-free approach that will encourage lower prices and wider adoption.”

Under the technology partnerships, MStar, Novatek and Realtek each will develop a range of DisplayPort Adaptive-Sync-ready scalers to complement the new monitor product cycle in 1Q15. Monitors equipped with such DisplayPort Adaptive-Sync-aware scalers will allow contemporary AMD Radeon graphics cards to synchronize display refresh rates and GPU framerates via Project FreeSync to enable tearing and stutter-free gaming along with low input latency.

The new scalers from MStar, Novatek and Realtek also will give monitor vendors access to a comprehensive set of features not available with other dynamic refresh technologies. Example features include: picture scaling, on-screen display (OSD), HDMI/DVI inputs for legacy users and DisplayPort High Bit Rate audio.

GaN-on-silicon substrate patent investigation

LONDON, ENGLAND: GaN-on-Si technology appeared naturally as an alternative to GaN-on-Sapphire—the main stream technology for LED applications. Today, despite potential cost benefits, the mass adoption of GaN-on-Si technology for LED applications remains unclear.

Most major LED makers have a patenting activity related to GaN-on-Si technology, but so far, few have made it the core of their strategy and technology roadmap. Contrary to the LED industry, we expect GaN-on-Si to be widely adopted by Power Electronics and RF applications because of its lower cost and CMOS compatibility.

The growth of GaN-on-silicon substrate was first reported in the early-1970s (T. L. Chu et al., J. Electrochemical Society, Vol. 118, page 1200), since the early 1990s more and more academics and industrials have been involved in developing this technology. GaN-on-Si technology is now poised for a list of technical challenges.

The high lattice mismatch between GaN and Si results in a high defect density in epitaxial layers (dislocations). The high thermal expansion coefficient (TCE) mismatch between GaN and Si leads to a large tensile stress during cooling from the growth temperature to room temperature. The tensile stress causes film cracking and a concave bending of the wafer (warpage). These factors combine to make both dislocation density and crack/warpage reduction a challenging task.

This patent investigation covers patents published worldwide up to December, 2013. The patents addressing the above mentioned challenges have been selected, and an in-depth analysis of patent holders and corresponding patented technologies is provided. This report does not include patents related to active layers or GaN-based devices.

Fundamental patents describing a gallium-nitride-based compound semiconductor grown on a silicon substrate were filed before the 1990s with the most significant assigned to TDK and Fujitsu. In the early 1990s, Toyoda Gosei and the University of Nagoya filed the first concepts of a buffer layer for improving the crystallinity of GaN. Those fundamental patents have been followed by an ever increasing number of applications since 1995 as more companies competed in GaN-on-Si technology to meet the technological challenges, the market demand and to lower manufacturing costs.

Currently, the patented technologies reflect the significant improvements that have been made on key material issues such as dislocation density reduction and stress management for preventing cracks and warpage of the wafer. According to our analysis, GaN-on-Si IP is mature enough to initiate mass production.

Friday, September 19, 2014

FinFET wafer demand to grow 60 percent over next four years

USA: Rolling out a new semiconductor technology always has its challenges, and it's also usually accompanied by speculations and surprises.

In 2011, at the 22nm process technology node, Intel surprised the semiconductor industry by introducing a three dimensional transistor structure, which Intel calls Tri-Gate, but is more commonly referred to in the industry as FinFETs.

There are only a few players expected to deliver FinFET manufacturing technology in the next few years, two IDM/foundries and two dedicated foundries.

Due to the electronic market shift to smartphones and tablets, how technology is applied and marketing strategy play a bigger role than just technology itself.  During the first 12 months of introduction, FinFET foundry demand at 14nm will see relatively small volumes.

Intel is now rolling out its second generation Tri-Gate technology as the foundries begin to run customer products on their 14nm FinFET processes.  Did Intel's early rollout set a new bar for the industry? Is FinFET transistor technology going to change the market positioning of computing and mobile market players?

Will the ramp of FinFET manufacturing capacity shift the market dynamics?  Will it change the foundry landscape?  FinFETs would have to set off a revolutionary change in the smartphone, tablet or convertible market in order for the rollout of 16nm/14nm to significantly change the foundry market share landscape.

However, Semico believes that once the communication market makes the transition to FinFET transistors, volumes will ramp significantly in 2017.  FinFET wafer demand will grow at a CAGR of almost 60 percent over the next four years.

Mentor Graphics and Lumerical unify optical design and simulation flow

WILSONVILLE, USA: Mentor Graphics Corp. announced an integration with Lumerical's INTERCONNECT to enable new silicon photonics design methodologies that leverage the Pyxis and Calibre platforms.

With the INTERCONNECT integration, users are now able to perform optical circuit simulation directly from the Pyxis Schematic.

With this integration, users can capture a photonic design and testbench, set up optical simulation parameters for transient and frequency analysis, perform simulation, and view results interactively from the Pyxis Schematic simulation cockpit.  This not only delivers a tremendous boost in productivity, but it also leverages the existing integration to high-capacity EZwave waveform viewer.

While traditionally used as a viewer for mixed-signal waveforms in the electrical time domain, the EZwave viewer, which includes a built-in waveform-based calculator, an eye diagram tool, and TCL scripting, is also ideal for processing optical simulation results.

Complementing the Pyxis Schematic in the Pyxis custom IC design platform is Pyxis Implement, a tool for layout design.  Well renowned for its all angle editing capabilities, Pyxis Implement with schematic-driven layout enables users to quickly place and assemble photonic PCells using connectivity-driven waveguide routing with radial and adiabatic bends, as well as S-bend support.

To complete this full-flow silicon photonics design methodology, Calibre tools perform DRC, LVS, lithography simulation, and smart-fill, ensuring photonic components meet the designed intent through the manufacturing process.

Samsung mass producing industry’s first 20nm 6Gb LPDDR3 mobile DRAM

SEOUL, SOUTH KOREA: Samsung Electronics Co. Ltd has begun mass producing its six gigabit (Gb) low-power double data rate 3 (LPDDR3) mobile DRAM, based on advanced 20 nanometer (nm) process technology. The highly-efficient new mobile memory chip will enable longer battery run-time and faster application loading on large screen mobile devices with higher resolution.

Samsung’s new 6Gb LPDDR3 has a per-pin data transfer rate of up to 2,133 megabits per second (Mbps). A 3GB (gigabyte) LPDDR3 package, which consists of four 6Gb LPDDR3 chips, can be easily created for use in a wide range of mobile devices. Also, the package greatly strengthens our product portfolio for premium mobile applications.

The new 3GB package is more than 20 percent smaller and consumes about 10 percent less energy than the currently available 3GB package with 6Gb LPDDR3 chips fabricated using Samsung’s previously lowest process technology. This results in a mobile memory that is ultra-small, incredibly thin, lightning fast and significantly more power-efficient.

Utilizing Samsung’s new 20 nanometer process also brings more than a 30 percent productivity gain, compared to the previous process. Samsung first applied 20 nanometer technology on 4Gb DDR3 for PCs in March, for the first time in the industry, and has now expanded its use to include the company’s mobile DRAM.

In the future, Samsung will continue to introduce more advanced 20nm mobile DRAM products to further strengthen its product line-up and maintain its leadership in the high-density mobile DRAM market, as the market expands with more feature-laden flagship smartphones, high-end tablets and wearable devices.

AT&S, Soundchip, and ST craft innovative bionic ear

LEOBEN, AUSTRIA & GENEVA, SWITZERLAND: AT&S, a leader in advanced packaging solutions, Soundchip SA, a Swiss-based innovator in wearable sound technology, and STMicroelectronics announced their collaboration in innovating a bionic hearing module that, when installed into a personal audio device, delivers an amazing wearable sound experience controlled at the ear by the wearer and software intelligence.

Personal audio devices, like an MP3 player or smartphone, equipped with the bionic hearing module, provide wearers with the ability to electronically “open” and “close” their ears to ambient sound conditions, or even to augment ambient sound with programmed audio from a connected smart device.

This capability can fully protect wearers from noise in situations where the ambient sound is too loud, or to open the ear for natural conversation with others, without having to remove the audio device, suffer from the discomfort of occlusion, or worse, the pain of loud noise.

The bionic hearing module integrates a broad spectrum of advanced electronics to further enhance the on-the-go audio experience, including head-tracking and other sensing, to enable exciting new features, including augmented-audio guidance and biometric monitoring.

The multi-mode audio capabilities of the bionic hearing module are enabled through the use of HD-PA technology developed by Soundchip. Their implementation in a compact form factor is made possible through the use of patented Soundstrate® technology, which enables the efficient combination of electronic, acoustic, and transmission means within a single, compact mechanical structure.

The semiconductor components in the bionic hearing module comprise the latest Motion and Audio MEMS (Micro-Electro-Mechanical System) components from STMicroelectronics, an HD-PA®-compliant Audio Engine for zero-latency sound processing, and an ultra-low-power STM32 MCU from ST’s industry-leading portfolio of more than 500 32-bit ARM® Cortex®-M-core microcontrollers.